The present claimed invention relates to the field of semiconductor packaging. More particularly, the present claimed invention relates to a low cost process for the formation of a package which is of the same size as the IC chip.
Semiconductor chips, commonly referred to as xe2x80x9cintegrated circuitsxe2x80x9d are an essential component of any electronic devices. These chips are usually mounted on a substrate which is also equipped with terminals for the electrical connectivity with the external world. These substrate could be either a single layer metal leadframe or a multi-layer printed wire board or likewise. Besides providing means for external electrical connectivity, these substrates also provide mechanical support to the chips. Encapsulation ensures protection of the chip from harsh physical and environmental factors. The interconnection between the chip and its supporting substrate is commonly referred to as xe2x80x9cfirst levelxe2x80x9d assembly. Several approaches exist for the first level assembly of chip to a supporting substrate. These include so called xe2x80x9cWire-bondingxe2x80x9d, xe2x80x9cTape Automated Bonding (TAB)xe2x80x9d and xe2x80x9cFlip Chipxe2x80x9d approaches. An encapsulated chip which is equipped with terminals for interconnection to the external world is often referred to as a chip package.
The approach for the first level connection between the chip and the substrate has strong ramifications on the overall package size, performance and reliability. In a electronic device circuit, several packages are interconnected using a common substrate. A large package size increases the distance between each chip and other chips or between each chips and other elements of the circuit. These larger distances result in longer delays in the transmission of electrical signals between chips. Consequently, the entire device is slowed down. Therefore, a reduction in package sizes leading to compact assembly can permit faster operation and therefore improved performance.
The approach used for the first level assembly of the chip to the substrate also influences the capacitances and inductances associated with the chip-to-substrate connections. Interconnections which result in large values of capacitances and inductances may result in large signal transmission delays, large switching noise and therefore performance degradation. Thus, lowering the capacitive and inductive parasitics associated with first level assembly is highly desirable.
The semiconductor chip, substrate and the encapsulant is usually made of materials which have very different material properties. Specifically, the semiconductor chip, which usually consists of silicon, has very different thermal expansion properties from the substrate materials, which can be a printed wiring board, metal lead frame or a ceramic substrate or the encapsulant material which usually consists of a epoxy resin. During the operation of the device, the electrical power dissipated within the chip tends to heat the chip and the substrate so that the temperature rises each time the chip is turned on. The chip and substrate material expand by different amounts each time the temperature increases. This causes electrical contacts on the chip to move relative to the electrical contacts on the substrate as the temperature of the chip and substrate changes. This relative movement deforms the electrical interconnections between the chip and substrate and places them under mechanical stress. Such stresses are generated each time the device is turned on and off. Such repeated exposure to stress may lead to breakage of the electrical interconnections.
In wire-bonding, the substrate has a top surface with a plurality of electrically conductive contact pads disposed in a ring-like pattern. The chip is secured to the top surface of the substrate at the center of the ring-like pattern, so that the chip is surrounded by the contact pads on the substrate. The chip is mounted in a face-up disposition, with the back surface of the chip glued to the top surface of the substrate. The front surface of the chip faces upward, and fine wires are connected between the contacts on the front face of the chip and the contact pads on the top surface of the substrate.
Wire-bonding ordinarily can only be employed when the chip I/O pads are distributed along the periphery of the chip and the substrate connection pads surround the chip in a ring-like configuration. Furthermore, wire-bonding requires a minimum pad size of 75 microns on a side and becomes non-feasible if the relative spacing between the chip pads decreases below 50 microns. With the ever increasing number of gates in IC chips the I/O counts are also increasing. Distribution of these increasing number of I/O pads along the periphery without increasing the Si chip size is posing a big challenge. Distribution of the I/O pads on the entire surface of the chip provides a more efficient configuration but wire-bonding cannot be employed for such cases. In addition, a wire bond is associated with a high inductance values. Thus, for circuits which involve simultaneous switching of a large number of gates, as is the case in present generation of microprocessors, high inductances of the wire bonds lead to a large switching noise. Wire bonds usually fan out from the chip to the substrate. Therefore, overall package size increases considerably relative to the chip size. Therefore, from the compactness standpoint, too, wire-bonding does not provide an optimal first level assembly process.
Assembly using wire-bonding require numerous process steps. For example in the formation of an overmolded wire-bonded Ball Grid Array package, some of the major steps consist of separating individual chips from the semiconductor wafer by sawing the wafer using a diamond impregnated saw. The wafer is usually mounted on a sticky polymer base so that the sawed chips remain stuck to the tape. Individual sawed chips are then attached to a substrate in a face-up configuration using a polymeric adhesive or a solder type of low melting point material. Usually, polymeric adhesives epoxies which are filled with metal flakes for good thermal and electrical conductivity are used for this attachment process. The adhesive joints are cured in an oxygen-free inert environment at elevated temperatures. Usually, the substrates have multiple repetitive units so as to process multiple chips. Then, the substrates with the attached dice are wire-bonded and then encapsulated. After the encapsulation process, solder balls are connected to the bottom face of the surface. These solder balls provide the external connectivity. After this step the individual Ball Grid Array packages are separated by sawing them off from the rest of the substrate carrier.
Tape automated bonding (TAB) requires a flexible tape with metal leads mounted on a polymer film. Usually, the tape leads fan out from the chip pads to the substrate connection pads. Therefore, the package is considerably larger than the chip. The flexible tape represents a new layer for interconnection and considerably adds to the cost of the package. This also requires deposition of excess metal in the form of bumps either on the connection regions of the leads or the chip pads. This is an additional process step and require processes similar to those used for IC fabrication such as lithography, etching and likewise. This adds to the cost of the process. Also, as in wire-bonding in TAB assembly, individual chips need to be sawed off from the wafer. Then these chips are bonded to a flexible tape which contains metal traces for external connectivity. Bonding a single lead at a time slows down the assembly cycle time considerably, thereby increasing the cycle time and the cost. Therefore, usually all the leads are bonded simultaneously to the chip pads in what is referred as xe2x80x9cGang Bondingxe2x80x9d process. This requires very tight control of the planarity of the tape leads and the chip pads connection sites. The long TAB leads also have high inductances and therefore lead to large switching noises in fast digital circuits. From a mechanical stress standpoint, flexible tape represents a good solution because the tape can deform and absorb the stress thereby increasing the reliability of the joints.
In a flip-chip process, usually the I/O pads are distributed on the entire surface of the chip. This enables placement of a larger no of I/O pads at a increased pitch without increasing the size of the silicon chip. The I/O pads are deposited with metal bumps of materials which can melt at bonding temperatures and fuse with the substrate pad materials. As in the case with wire-bonding and TAB, individual chips have to sawed-off from the wafer before these are bonded to the substrate. The chip is bonded face-down such that the active face of the chip with the connection pads face the top surface of the substrate. The metal bumps on the chip pads provide a separation between the chip and the substrate. These bumps are considerably shorter in length than a wirebond or a TAB lead. Therefore, inductances associated with these joints are considerably lower. These joints, which are composed of stiff metal bumps, pose a reliability challenge. When mechanical stress builds-up due to temperature changes and a resulting expansion mismatch between the chip and the substrate, the metal joints unlike TAB tape, cannot deform and relieve the stress. This leads to breakage of the joints. In order to improve the reliability, an epoxy resin material is dispensed in the region between the chip and the substrate. This so called xe2x80x9cunderfillxe2x80x9d material encapsulates the exposed regions of the metallic joints and acts as a stress buffer thereby significantly improving the reliability. However, this underfilling step is an additional process and adds to the assembly cost by increasing the process cycle time as well number of constituent layers.
Several different approaches exist in the prior art for the formation of compact packages. Two representative examples, spanning the range from large to nearly chip size, are given here. The first one is what is referred to as an overmolded ball grid array (BGA) package 100, schematically shown in FIG. 1a. In this package, the chip 101 is bonded to a printed wiring board (PWB) substrate 102 in a face-up configuration. The PWB substrate has multiple layers of metal traces which are used for connecting the peripherally distributed chip contact regions 103 on the chip 101 to the external solder balls 104 which are distributed across the bottom face of the PWB substrate. Wirebonds 105 connect the chip connection pads to top layer traces on the PWB. The top half containing the chip and the wirebonded regions are encapsulated in an epoxy resin system 106.
The second example is a compact package shown schematically in FIG. 1b. In this package integrated circuit chip 200 has an elastomeric overlayer 201. Chip contact ports 202 of the integrated circuit chip 200 are exposed and not covered with the elastomeric overlayer 201. Metal traces or leads present in a flexible tape 203 are used to re-distribute the I/O ports 202 from the periphery of the chip 200 to the central region of the elastomeric overlayer 201. One end of the leads or traces in the flexible tope 203 connects to one of the I/O ports 202 via a wire bond, whereas the other end is routed over the elastomeric overlayer 201 and is deposited with a Ni metal bump 204 for external connectivity.
The overmolded BGA package shown in FIG. 1 involves wire-bonding, and due to the fan-out of the wire bonds from the chip to the substrate, the resultant package size is large. The package shown in FIG. 2 in comparison presents a much more compact size. Both these configurations use long wires or leads for connection of chip I/O ports to the substrate. Thus, inductances are generally high. Both these packages are applicable only to those chips which have peripherally distributed I/O pads. These packages require several different material layers besides the chip. The assembly process starts with the sawing-off of the individual chips from the wafer. Then the chips are mounted on carriers for furthering processing. In the overmolded BGA package, the PWB substrate needs to be custom designed to match the chip I/O pad distribution. Similarly, in the compact package of FIG. 2, the flexible tape needs to be custom designed for each chip design. In these approaches, each of the IC chips is separated from the wafer and bonded to individual sites on a substrate or tape. Although the substrate or tape can be enlarged so as to contain multiple such individual chip connection sites, still there is a size restriction on the substrate due to the limitation of the equipment which is needed for assembly of these substrates. Consequently, the substrates could contain only a small number of such individual chip sites and therefore, only a small number of chips can be assembled in one step.
Thus, a need exists for a method of forming a chip package which has fewer steps, uses fewer materials and can use the existing conventional equipment and infrastructure. Still another need exists for an assembly method whereby large numbers of chips from a wafer can be processed simultaneously. Also, a need exists for an assembly method which does not require mounting of the individual chips on substrates or frames for processing. Still another need exists for an assembly method wherein a large number of chips which are connected together on a wafer can be mounted in one region on a substrate and then encapsulated and processed to yield individual compact packages. Still another need exists for a package which offers low inductance. A further need exists for a package which is fabricated from the conventional materials and procedures so that the assembly costs are lower.
The present invention provides a method and structure for a chip package wherein multiple chips which are connected to each other are assembled and encapsulated together and then sawed to form individual chip packages.
Specifically, in one embodiment, the semiconductor chip package comprises a semiconductor chip having a plurality of contact pads; a first dielectric layer overlying the chip and containing a hole, the hole overlying one of the contact pads; a metal trace extending from a location inside the hole along a surface of the first dielectric layer, the metal trace being in electrical contact with the pad; a second dielectric layer overlying the first dielectric layer and metal trace and containing a second hole, the second hole overlying the trace and being lined with a metal layer in electrical contact with the trace; a first metal bump formed in the second hole and extending above the second dielectric layer; an encapsulant layer overlying the second dielectric layer, the first metal bump extending through the encapsulant layer; and a second metal bump formed on top of and in electric contact with the first metal bump.
In addition, the invention includes a method of manufacturing semiconductor chip packages. The method includes providing a semiconductor wafer containing a plurality of chips; forming a first dielectric layer over a surface of the wafer; forming a first plurality of holes in the dielectric layer, the holes corresponding with the locations of contact pads on the surface of the wafer; depositing a first metal layer on a surface of the first dialectic layer; patterning the first metal layer to form traces, each of the traces extending from one of the first plurality of holes; depositing a second dielectric layer over the first dielectric layer and the first metal layer; forming a second plurality of holes in the second dielectric layer, each of the second plurality of holes corresponding with the location of at least one of the traces; depositing a second metal layer over the second dielectric layer, the second metal layer extending into the second plurality of holes; removing a portion of the second metal layer, leaving the second metal layer in the second plurality of holes; forming a first plurality of metal bumps in the second plurality of holes; depositing an encapsulant layer covering the first plurality of metal bumps; removing a portion of the encapsulant layer so as to expose a portion of the bumps in the first plurality of bumps; forming a second plurality of bumps on the exposed portions of the first plurality of bumps; and separating the chips by sawing the wafer, the first and second dielectric layer and the encapsulant layer, thereby producing the semiconductor chip packages.
In another embodiment, wafer is sawed into sections each containing a plurality of chips after the first plurality of metal bumps has been formed. The method then includes depositing an encapsulant layer covering the first plurality of metal bumps; removing a portion of the encapsulant layer so as to expose a portion of the bumps in the first plurality of bumps; forming a second plurality of bumps on the exposed portions of the first plurality of bumps; and separating the chips by sawing the segments, thereby producing the semiconductor chip packages.
In a different embodiment, the first plurality of metal bumps are directly deposited directly over the chip contact pad regions. As in the previous embodiments, the method then includes depositing an encapsulant layer covering the first plurality of metal bumps; removing a portion of the encapsulant layer so as to expose a portion of the bumps in the first plurality of bumps; forming a second plurality of bumps on the exposed portions of the first plurality of bumps; and separating the chips by sawing the segments, thereby producing the semiconductor chip packages. Alternatively, as described above, the wafer can be sawed into multi-chip sections after the deposition of the first metal bumps and before the encapsulation process.
The present invention provides a chip package which is compact, associated with low inductance, has good reliability and can be fabricated at a low cost.
These and other objects and advantages of the present invention will become apparent to those of ordinary skill in the art after reading the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.